SanDisk Goes Beyond HBF: Patent Bonds Processor onto NAND Tile, with HBM Stacks on Shared Interposer
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SanDisk Goes Beyond HBF: Patent Bonds Processor onto NAND Tile, with HBM Stacks on Shared Interposer

　　While SanDisk is speeding up the development of High Bandwidth Flash (HBF), a next-generation architecture that vertically stacks NAND, the company is also advancing additional memory concepts aimed at addressing structural capacity constraints.　　According to a U.S. patent (US 12,430,274 B2) filed and published by SanDisk earlier, the proposed design integrates a multi-core processor directly onto a CBA (CMOS Bonded to Array) memory tile — which itself combines a large NAND flash array with a CMOS logic layer.　　The integrated stack is then mounted on an interposer, with stacks of HBM semiconductor dies affixed around one or more sides of the combined stack, SanDisk notes.　　Rationale Behind the Design　　The design rationale behind SanDisk’s approach, as noted by Wccftech, is partly driven by the inherent limitations of HBM, particularly its relatively constrained capacity, as well as the challenges that HBF has yet to fully address, including latency, power efficiency, and system-level integration complexity.　　To overcome HBM’s capacity ceiling, SanDisk previously introduced its HBF architecture, which adopts a similar concept to HBM by vertically stacking multiple layers of NAND flash and connecting them via through-silicon vias (TSVs) to form a unified memory stack, according to Wccftech.　　While current HBM solutions typically offer 32–64GB per stack, HBF is designed to scale significantly higher, with reported capacity reaching up to 4TB. According to SanDisk, HBF is capable of closely matching HBM’s bandwidth while delivering 8-16x the capacity of HBM at a similar cost.　　However, despite NAND offering higher capacity at a lower cost, Wccftech also points out that it is positioned further from the compute die, resulting in slower data access compared to DRAM-based architectures. In response, SanDisk’s latest patent, as highlighted by the report, proposes a 3D stacking design in which a NAND flash tile, built using a CBA structure, is positioned beneath a compute tile such as an AI accelerator or GPU.　　Under this configuration, HBM DRAM would still be integrated on the same interposer, but would serve a distinct role within the overall memory-compute hierarchy, according to Wccftech. As highlighted by the report, this architecture allows HBM to handle immediate, high-speed memory operations, while the NAND flash layer within the memory tile is used for read/write-intensive workloads and large-scale data storage.
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Release time：2026-06-23 10:58 reading：124 Continue reading>>
Intel Taps <span style='color:red'>SK</span> hynix Ex-CEO as Foundry EVP to Lead Advanced Packaging Push as EMIB, HBI Scale Up
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Intel Taps SK hynix Ex-CEO as Foundry EVP to Lead Advanced Packaging Push as EMIB, HBI Scale Up

　　Intel CEO Lip-Bu Tan is accelerating the company’s foundry ambitions, continuing to recruit seasoned talent from across the chip industry. The latest move is the appointment of Seok-Hee Lee as Executive Vice President of Intel Foundry, according to an Intel announcement on June 18.　　Notably, Lee joins Intel after serving as president and CEO of SK On and previously leading SK hynix. A semiconductor industry veteran, he also held engineering leadership roles at Intel and in academia, bringing deep expertise in advanced process technologies and large-scale manufacturing, according to the press release.　　Reporting directly to Tan, Lee will oversee advanced packaging, system integration, back-end technology development, and manufacturing, as noted by the company. Intel said the appointment is aimed at strengthening its system-level innovation capabilities and supporting the next phase of its foundry expansion.　　Tan also underscored Lee’s pivotal role in advancing Intel’s next-generation packaging strategy.“As we prepare to scale advanced packaging technologies, including EMIB-T and HBI, for high-volume production, Seok-Hee is the ideal leader to drive the growth of this strategically important business,” Tan said.　　The appointment, as Reuters points out, comes after U.S. President Donald Trump announced earlier that Apple had agreed to collaborate with Intel on designing and manufacturing chips in the United States, providing a potential boost to Intel’s foundry business.　　A previous Reuters report, citing The Information, also reported that Google has tapped Intel to manufacture more than 3 million TPUs in 2028, while NVIDIA is evaluating Intel’s 18A process and advanced packaging technologies for a next-generation multi-die GPU design.　　Meanwhile, Intel Foundry EVP Naga Chandrasekaran will continue reporting to CEO Lip-Bu Tan, overseeing front-end technology development and manufacturing as Intel accelerates the ramp of Intel 18A, Intel 14A and future process nodes. He will also retain responsibility for design enablement and customer-facing business operations, supporting Intel Foundry’s long-term growth.　　Intel’s Talent Offensive Continues　　Lee’s appointment marks the latest in a series of high-profile hires since Lip-Bu Tan took the helm at Intel. Reuters notes that the company bolstered its foundry ambitions in April by recruiting Samsung foundry veteran Shawn Han to support its contract manufacturing business.　　The hiring drive began earlier. In late 2025, Intel brought in former TSMC senior vice president Wei-Ren Lo as executive vice president overseeing manufacturing and packaging amid controversy surrounding alleged sub-2nm trade secrets. Intel said Lo’s return was part of its broader transformation effort, with the veteran executive bringing back nearly two decades of experience gained at Intel before joining TSMC.
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Release time：2026-06-22 10:51 reading：152 Continue reading>>
<span style='color:red'>SK</span> hynix Reportedly Pulls Forward HBM4E Sample Timeline, Eyeing June–July Shipments to Key Customers
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SK hynix Reportedly Pulls Forward HBM4E Sample Timeline, Eyeing June–July Shipments to Key Customers

　　Samsung announced the start of HBM4E sampling in late May and later unveiled an HBM5 mock-up for the first time at COMPUTEX 2026. Against this backdrop, rival SK hynix is also stepping up its next-generation HBM push, with South Korean media outlet Newsis reporting that the memory giant has secured positive results in HBM4E development and is nearing sample shipments to key customers.　　Notably, certain analysts cited by the report expect SK hynix to begin HBM4E sample shipments as early as this month, or by July at the latest. The company had previously guided that sampling would start in the second half of the year, suggesting the timeline is now being pulled forward, the report adds.　　As Newsis notes, next-generation HBM is highly customized for customers, and earlier sample shipments enable faster performance validation and optimization—ultimately translating into a strategic edge in securing final mass production orders.　　Beyond sampling timelines, broader supply and pricing dynamics are also shifting, which may give early movers key advantages. According to TrendForce, as the market enters 2Q26, negotiations between buyers and suppliers have shifted toward HBM4 supply agreements for 2027, which is expected to become the market’s mainstream project generation. The shift underscores how both Samsung and SK hynix are accelerating HBM4 and HBM4E development amid tightening market cycles.　　SK hynix HBM4E Specs Under Spotlight　　As highlighted by Newsis, SK hynix’s HBM4E is likely to be used in NVIDIA’s next-generation AI accelerator, Rubin Ultra, set for release next year. In line with this platform upgrade, TrendForce notes that NVIDIA’s Rubin Ultra is expected to further increase HBM capacity per GPU to 384GB.　　Against this backdrop of rising system-level requirements, HBM4E specifications are also being pushed higher across the stack. According to Newsis, SK hynix’s HBM4E core die is expected to adopt a 1c DRAM process node, compared with the 1b node used in HBM4. In addition, The Chosun Daily previously reported that the company is likely to use TSMC’s 3nm process for its HBM4E logic die, aiming to challenge Samsung’s 4nm design.　　On the competitive front, Samsung Electronics completed the world’s first shipment of HBM4E samples in late May, supplying them to NVIDIA, according to Yonhap News.　　Samsung’s HBM4E combines a 1c DRAM core die with a 4nm foundry-based base die, delivering speeds of up to 14Gbps per pin and peaking at 16Gbps, equivalent to a maximum bandwidth of 4TB/s, the report notes.
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Release time：2026-06-16 10:43 reading：362 Continue reading>>
Tesla Elon Musk Discusses TeraFab at ASML Conference; Project Expected to Spur EUV Tool Orders
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Tesla Elon Musk Discusses TeraFab at ASML Conference; Project Expected to Spur EUV Tool Orders

　　Elon Musk is expanding his ambitions beyond EVs, AI, and space technology with TeraFab, a large-scale semiconductor manufacturing project in Texas. According to CNBC, during an ASML conference on Thursday, Tesla CEO Elon Musk outlined his TeraFab vision. As the only provider of a crucial EUV machine, ASML is widely expected to become a key supplier for the Texas-based fabrication plant.　　Joining remotely at ASML’s annual technology conference, Musk took part in a fireside chat with CEO Christophe Fouquet. While the event was limited to employees, ASML confirmed Musk’s participation, the report states.　　ASML also signaled support for the initiative. As noted by Reuters, the company said that Musk and his team are becoming part of the broader semiconductor ecosystem and that many companies, including ASML, will collaborate on the project.　　For the project, SpaceX and its partner Tesla will invest an initial US$55 billion, with total investment potentially rising to US$119 billion if fully built out, as noted by Reuters.　　TeraFab Fuels Equipment Demand Across the Supply Chain　　In May, ASML CEO Christophe Fouquet said he had spoken directly with Elon Musk about the TeraFab semiconductor project, according to Tom’s Hardware, citing Reuters. While Fouquet did not disclose details of the discussions, he said projects such as TeraFab and Starlink are expected to place growing pressure on equipment suppliers’ capacity in the coming years.　　Maeil Business Newspaper also notes that expectations for a surge in equipment demand have risen after Musk discussed the TeraFab project at the ASML Technology Conference. The report adds that ASML’s core equipment is expected to be essential to the project.　　South Korean equipment makers are also seeking to capitalize on the opportunity. According to Seoul Economic Daily, Hanmi Semiconductor announced on June 12 that it will invest KRW 50 billion in SpaceX. The report says Hanmi aims to strengthen ties with SpaceX and position itself to supply key equipment for TeraFab.　　Interest in the project has been building for months. According to Bloomberg, Musk’s team had reportedly contacted major chip equipment suppliers, including Applied Materials, Tokyo Electron, and Lam Research, regarding the planned facility. Sources said staff working for the Tesla-SpaceX venture had requested pricing and delivery information for a range of semiconductor manufacturing tools.
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Release time：2026-06-15 10:48 reading：352 Continue reading>>
<span style='color:red'>SK</span> hynix Reportedly to Double DRAM Capacity to 1M Monthly Wafers by 2030, Speeds Yongin Expansion
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SK hynix Reportedly to Double DRAM Capacity to 1M Monthly Wafers by 2030, Speeds Yongin Expansion

　　TrendForce　　SK hynix is reportedly preparing a major DRAM capacity expansion. According to The Elec, the company has shared plans with key suppliers to nearly double its DRAM wafer production capacity by 2030–2031 from current levels. The plan aligns with comments made by SK Group Chairman Chey Tae-won at Computex 2026, where he said the company would “double overall wafer production capacity within five years at full speed.”　　The report says SK hynix aims to raise monthly DRAM wafer capacity from about 550,000 wafers today to roughly 1 million wafers by 2030. The current figure includes around 200,000 wafers per month from its Wuxi fab in China.　　Much of the expansion will be centered on the Yongin Semiconductor Cluster. According to the report, SK hynix plans to divide its first Yongin fab into six cleanrooms and has moved up the first equipment installation schedule from May 2027 to February 2027. The fab is expected to add 360,000 wafers per month of DRAM capacity by the first half of 2030.　　SK hynix is also expanding its M15X fab in Cheongju. The report says the facility is scheduled to begin operations in the second half of 2026 with an initial capacity of 40,000 wafers per month, rising to about 80,000 wafers per month in 2027.　　Combined with the additional output from Yongin, SK hynix’s total DRAM wafer input capacity could approach 1 million wafers per month between 2030 and 2031, according to the report.　　Notably, all newly added capacity is currently designated for DRAM production, the report notes. For NAND flash, SK hynix is expected to focus on technology upgrades, such as increasing layer counts, rather than significant capacity expansion.　　Equipment Suppliers See Near-Term Gains, but Remain Cautious　　The expansion of the Yongin Semiconductor Cluster is drawing a growing number of semiconductor equipment and materials suppliers. According to iNews24, equipment and materials suppliers continue to move into the Yongin Semiconductor Cluster. South Korean materials, parts, and equipment firms, along with ASML, Lam Research, and Tokyo Electron Korea, have either relocated or are in the process of moving in.　　However, The Elec notes that suppliers remain cautious about execution given the scale and pace of the expansion plan. Supplier sources cited by the report said the increased investment is expected to provide a meaningful near-term boost for equipment and materials vendors, though achieving the full expansion target will ultimately depend on whether market demand remains strong enough to support it.　　Samsung Also Accelerating DRAM Expansion　　As for Samsung, according to Digital Daily, Samsung Electronics is accelerating DRAM capacity expansion at its P4 fab in Pyeongtaek by bringing forward its investment schedule. The report says Samsung’s DRAM investment next year could increase by roughly 10,000 wafers per month above previous estimates. Some industry observers also expect Samsung to begin issuing purchase orders for the P5 line from the second quarter of next year, potentially supporting investment equivalent to 150,000 wafers per month in 2027.
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Release time：2026-06-08 10:46 reading：526 Continue reading>>
<span style='color:red'>SK</span> Chair Sees Memory Shortage Through 2030, Eyes Capacity Doubling and Stronger TSMC, Taiwan Ties
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SK Chair Sees Memory Shortage Through 2030, Eyes Capacity Doubling and Stronger TSMC, Taiwan Ties

　　As next-gen HBM solutions has become a key focus at COMPUTEX amid surging AI demand, SK Group Chairman Chey Tae-won made a brief visit to the SK hynix booth on June 2 and spoke with the media. According to TechNews, Chey expects supply-demand tightness in the memory market to persist through 2030.　　Notably, he also said SK will make full efforts to expand production under tight supply conditions, targeting a doubling of total wafer capacity over the next five years, the report adds.　　Marking his first appearance at COMPUTEX, Chey noted that Taiwan has a highly complete AI supply chain and a strong partner ecosystem. As SK Group continues to expand its AI business, he stressed the need to deepen collaboration with more Taiwanese companies. Beyond TSMC, he said meetings with firms such as Foxconn and Asus are also part of this visit to better understand ongoing cooperation and explore ways to further strengthen partnerships, according to the report.　　SK hynix and TSMC have a long-standing partnership, particularly in logic die integration as custom HBM solutions become an emerging industry trend. As previously reported by The Chosun Daily, SK hynix is expected to adopt a 10nm-class 6th-generation (1c) DRAM process for the core die in its HBM4E, paired with a logic die built on TSMC’s 3nm node. For HBM4 supplied to NVIDIA this year, the company is said to be using a 10nm-class 5th-generation (1b) DRAM core die alongside a logic die based on TSMC’s 12nm process.　　Jensen Huang’s SK hynix Booth Visit Marks Another COMPUTEX Highlight　　It is also wort noting that NVIDIA CEO Jensen Huang also visited the SK hynix booth at COMPUTEX 2026 on June 2, meeting SK Group Chairman Chey Tae-won for the second consecutive day, following a dinner meeting the previous evening. According to Chosun Biz, after his keynote the day before—where he directly identified SK hynix as a supplier of next-generation HBM4—Huang toured the exhibition floor and reviewed the company’s latest memory products.　　During the visit, Huang joined Chey at the SK hynix booth to examine the showcased portfolio, including HBM4E wafers and chipset samples, which entered sampling at the end of last month, the report says. It also marked the first public unveiling of an HBM4E physical mock-up, according to Chosun Biz.
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Release time：2026-06-03 10:57 reading：530 Continue reading>>
Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–SanDisk Capex Reportedly Rises 40% YoY
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Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–SanDisk Capex Reportedly Rises 40% YoY

　　As South Korea’s memory giants shift focus toward 1c DRAM capacity expansion amid surging demand, Global Economic, citing German tech outlet ComputerBase, reports that the Kioxia–SanDisk alliance is moving fast to reassert its position in the NAND market, capitalizing on an investment gap as Samsung Electronics and SK hynix divert resources toward HBM.　　According to the reports, the U.S.–Japan NAND consortium is expected to execute total capital expenditure of $4.5 billion (about KRW 6.75 trillion) in the current fiscal year, marking a 41% year-on-year increase.　　Notably, a key focus of the alliance would likely be the 10th-generation NAND. Nikkei previously reported that Kioxia plans to begin mass production at its Kitakami site in Iwate Prefecture in 2026. However, given the jump to a 332-layer architecture—up from 218 layers in its 8th-generation devices—the company is expected to repurpose its newly operational Kitakami K2 facility, which began production in September, to support output, according to Nikkei.　　ComputerBase, cited by Global Economic, attributes the strong NAND demand supporting Kioxia–SanDisk’s investment to a structural shift in AI workloads: As AI moves from the training-heavy infrastructure build-out phase to large-scale inference deployment, demand is rising for high-performance, ultra-high-capacity storage.　　At the same time, storage is accounting for a growing share of hyperscaler data center capex, while SSD capacity per GPU is more than doubling year over year, the report notes. As a result, next-gen AI servers are increasingly being designed with tens of terabytes of storage per GPU, driving a sustained surge in NAND demand, the report adds.　　Fewer Layers, Comparable Density　　ZDNet also reports that in its recent earnings briefing, Kioxia identified the launch of 10th-generation BiCS NAND as a key priority for fiscal 2026 (April 2026–March 2027). The report adds that the company applies its proprietary BiCS (Bit Cost Scalable) architecture to its scaling roadmap, with the 10th-generation device delivering 59% higher storage density per unit area and a 33% improvement in data transfer speed compared with the 218-layer generation.　　According to ComputerBase, Kioxia’s stacking approach enables comparable density with fewer layers, translating into meaningful cost advantages. A lower stack height also simplifies vertical etching, reduces high-cost equipment runtime, and helps mitigate wafer warpage defects.　　Based on 3D NAND density estimates cited by Global Economic from ComputerBase, Kioxia / SanDisk BiCS10 is projected to reach 37.6Gb per square millimeter in QLC configuration, which would surpass Samsung Electronics’ upcoming 430-layer V10 TLC architecture at around 28.0Gb.　　Samsung, SK hynix Hold Back　　However, TrendForce indicates that major NAND Flash suppliers will add virtually no new production capacity in 2026, and it seems that South Korean memory players are taking a different approach with Kioxia and SanDisk.　　As highlighted by Global Economic, Samsung Electronics and SK hynix have both adjusted their 10th-generation NAND ramp-up schedules: Samsung has reportedly pushed back its V10 production timeline from the second half of 2025 to 2026, while SK hynix is targeting early 2027 for full-scale production.　　ZDNet also reports that Samsung Electronics had initially planned to begin mass production of its 430-layer 10th-generation NAND this year, but the timeline has been delayed to at least 2027, citing technical complexity and softer demand conditions. The report adds that Samsung is still reviewing investment timing, with no concrete equipment orders confirmed, and that SK hynix faces a similar situation.　　Global Economic notes that if the U.S.–Japan NAND alliance succeeds in lowering cost per terabyte and accelerating QLC enterprise SSD adoption, demand could shift more rapidly toward AI data center storage. Even so, Samsung and SK hynix remain competitive, supported by stable 9th-generation yields and strong enterprise SSD customer bases, the report adds.
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Release time：2026-06-01 10:45 reading：485 Continue reading>>
<span style='color:red'>SK</span> hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction
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SK hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction

　　As thermal management emerges as a key challenge for HBM, SK hynix has unveiled its iHBM solution, which integrates cooling elements (ICEs) directly into the HBM package. The company plans to adopt the technology in next-generation products, including HBM5, according to its press release.　　According to SK hynix, unlike conventional HBM designs that dissipate heat through the core die, iHBM integrates cooling elements (ICEs), made of thermally conductive, electrically non-conductive silicon-based materials, directly into the D2D PHY between HBM and GPUs, where heat is most concentrated. The company said the technology reduces thermal resistance by 30% and improves operating stability.　　As highlighted by SK hynix, the iHBM solution adopts a structural approach to thermal management by creating an additional heat dissipation path within the package. It also leverages the company’s wafer-level packaging (WLP) process and proven MR-MUF technology to enable stable high-volume manufacturing.　　In addition, its compatibility with existing System-in-Package (SiP) architectures allows customers to adopt the thermal solution with minimal design modifications, SK hynix adds.　　In terms of future roadmap, SK hynix plans to incorporate the iHBM solution into next-generation HBM products, including HBM5, with the goal of improving the stability and efficiency of HPC systems and AI data centers.　　Another Key Technology beyond Hybrid Bonding　　Alongside SK hynix’s latest iHBM solution, hybrid bonding is widely seen as a key approach to addressing heat dissipation challenges in 20-stack HBM, which, as previously reported by The Elec, are expected to become increasingly difficult.　　As explained in the report, hybrid bonding differs from conventional thermo-compression (TC) bonding, which connects chips through soldered micro-bumps. Instead, it bonds dielectric materials such as silicon dioxide (SiO₂) and copper through an annealing process at temperatures of roughly 200°C to 400°C.　　By heating and gradually cooling copper sealed within dielectric layers, thermal expansion and vertical pressure enable direct copper-to-copper diffusion bonding without reaching copper’s melting point, the report notes, adding this approach helps reduce thermal damage to semiconductor circuits while delivering improved thermal and electrical performance.
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Release time：2026-05-27 10:42 reading：633 Continue reading>>
Murata’s Type 1SC-NTN module achieves Skylo U.S. certification for cellular and non-terrestrial network connectivity
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Murata’s Type 1SC-NTN module achieves Skylo U.S. certification for cellular and non-terrestrial network connectivity

　　Murata announced today that its Type 1SC-NTN has received Skylo U.S. certification for its dual-mode cellular and non-terrestrial network (NTN) capabilities, making it the first ultra-compact resin mold module to achieve this recognition from an NTN service provider. The product seamlessly integrates the latest Rel-17 NTN standard, enabling satellite data communication capabilities without necessitating any hardware design changes. When paired with Skylo's NTN service, it extends the reach of satellite connectivity, ensures uninterrupted communication, and delivers a new class of solution for the demanding satellite IoT market.　　Murata’s Type 1SC is the world’s smallest form factor LTE Cat M/NB-IoT module with both global regulatory and NTN certification. It supports GPS/GNSS, OpenMCU, and Integrated SIM to support the applications that are defining today’s market, such as dual-mode cellular IoT. In addition to its unmatched size, low power, and cost-efficiency, its high level of integration accelerates time to market while lowering development and deployment costs for customers. Target uses include wearable, tracking, and medical monitoring devices, as well as M2M communication, smart meters, and other size-limited IoT edge products.
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Release time：2024-10-15 13:19 reading：1124 Continue reading>>
<span style='color:red'>SK</span>J：at are Crystals for
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SKJ：at are Crystals for

　　Chips are the brain of digital circuits, and the main function of crystal oscillators is to provide precise and stable clock signals for chips, which is extremely important for control circuits, especially for chips. Clock signals can enable various circuits to complete their functions, as well as synchronize electronic devices with peripheral controller devices.　　The position of crystal oscillators in digital circuits is indispensable, so if crystal oscillators are improperly selected or applied in circuits, the problems can be countless. Perhaps because of this, once the device malfunctions, the crystal oscillator is often the first suspect. But is this the only answer?　　If the chip cannot capture the frequency signal output by the crystal oscillator, there are many possibilities, such as problems with the chip itself (selection issues, quality issues, welding issues, etc.), incorrect crystal oscillator selection (referring to the mismatch between the crystal oscillator and the chip, such as frequency accuracy, working temperature range, load capacitance selection) The crystal oscillator itself is poor (quality is unqualified, the crystal oscillator is damaged in Ultrasonic welding, the crystal oscillator is broken, and its air tightness is damaged), and the crystal oscillator is improperly used in circuit applications (including faulty soldering, too long wiring, wrong pin identification, short circuit, open circuit, wrong selection of load capacitance, improper matching of external capacitance, excessive stray capacitance interference, motor interference, power interference, etc.).　　The most frequently asked question recently is: Just touch the crystal oscillator with your hand, what's going on in a while? Is the crystal oscillator broken?　　Based on experience, this situation is generally caused by improper application of crystal oscillators in circuits. It is recommended to check whether the accuracy of the actual output frequency of the crystal oscillator meets the chip requirements after power on. If there is a serious deviation in the crystal oscillator frequency, we generally recommend adjusting the size of the external capacitor to improve it. If the problem persists, please consult Jingkexin's official website customer service to further understand some special cases.
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Release time：2023-08-24 13:52 reading：3078 Continue reading>>

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